Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 292
Documentation Changes
15. Updates to Appendix G, Volume 3B
Change bars show changes to Appendix G of the Intel
®
64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 3B: System Programming Guide, Part 2.
------------------------------------------------------------------------------------------
...
G.10 VPID AND EPT CAPABILITIES
The IA32_VMX_EPT_VPID_CAP MSR (index 48CH) reports information about the capa-
bilities of the logical processor with regard to virtual-processor identifiers (VPIDs,
Section 25.1) and extended page tables (EPT, Section 25.2):
• If bit 0 is read as 1, the logical processor allows software to configure EPT paging-
structure entries in which bits 2:0 have value 100b (indicating an execute-only
translation).
• Bit 6 indicates support for a page-walk length of 4.
• If bit 8 is read as 1, the logical processor allows software to configure the EPT
paging-structure memory type to be uncacheable (UC); see Section 21.6.11.
• If bit 14 is read as 1, the logical processor allows software to configure the EPT
paging-structure memory type to be write-back (WB).
• If bit 16 is read as 1, the logical processor allows software to configure a EPT PDE to
map a 2-Mbyte page (by setting bit 7 in the EPT PDE).
• If bit 17 is read as 1, the logical processor allows software to configure a EPT PDPTE
to map a 1-Gbyte page (by setting bit 7 in the EPT PDPTE).
• Support for the INVEPT instruction (see Chapter 6 of the Intel
®
64 and IA-32 Archi-
tectures Software Developer’s Manual, Volume 3A and Section 25.3.3.1).
— If bit 20 is read as 1, the INVEPT instruction is supported.
— If bit 25 is read as 1, the single-context INVEPT type is supported.
— If bit 26 is read as 1, the all-context INVEPT type is supported.