Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 282
Documentation Changes
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Table A-7 Fixed-Function Performance Counter
and Pre-defined Performance Events
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86H 01H UNC_CYCLES_UNHAL
TED_L3_FLL_DISABL
E
Uncore cycles that at least one core is
unhalted and all L3 ways are disabled.
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Fixed-Function
Performance
Counter Address
Event Mask
Mnemonic Description
MSR_PERF_FIXED_
CTR0/
IA32_PERF_FIXED_CT
R0
309H Inst_Retired.Any This event counts the number of
instructions that retire execution. For
instructions that consist of multiple micro-
ops, this event counts the retirement of
the last micro-op of the instruction. The
counter continue counting during
hardware interrupts, traps, and inside
interrupt handlers
MSR_PERF_FIXED_
CTR1/
IA32_PERF_FIXED_CT
R1
30AH CPU_CLK_UNHALT
ED.CORE
This event counts the number of core
cycles while the core is not in a halt state.
The core enters the halt state when it is
running the HLT instruction. This event is a
component in many key event ratios.
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MSR_PERF_FIXED_
CTR2/
IA32_PERF_FIXED_CT
R2
30BH CPU_CLK_UNHALT
ED.REF
This event counts the number of
reference cycles when the core is not in a
halt state and not in a TM stop-clock state.
The core enters the halt state when it is
running the HLT instruction or the MWAIT
instruction.
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