Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 280
Documentation Changes
35H 02H UNC_ADDR_OPCODE
_MATCH.REMOTE
Counts number of requests from the
remote socket, address/opcode of
request is qualified by mask value
written to MSR 396H. The following
mask values are supported:
0: NONE
40000000_00000000H:RSPFWDI
40001A00_00000000H:RSPFWDS
40001D00_00000000H:RSPIWB
Match opcode/
address by
writing MSR
396H with
mask
supported
mask value
35H 04H UNC_ADDR_OPCODE
_MATCH.LOCAL
Counts number of requests from the
local socket, address/opcode of
request is qualified by mask value
written to MSR 396H. The following
mask values are supported:
0: NONE
40000000_00000000H:RSPFWDI
40001A00_00000000H:RSPFWDS
40001D00_00000000H:RSPIWB
Match opcode/
address by
writing MSR
396H with
mask
supported
mask value
...
42H 01H UNC_QPI_TX_HEADE
R.FULL.LINK_0
Number of cycles that the header
buffer in the Quickpath Interface
outbound link 0 is full.
...
42H 04H UNC_QPI_TX_HEADE
R.FULL.LINK_1
Number of cycles that the header
buffer in the Quickpath Interface
outbound link 1 is full.
...
67H 01H UNC_DRAM_THERM
AL_THROTTLED
Uncore cycles DRAM was throttled
due to its temperature being above
the thermal throttling threshold.
80H 01H UNC_THERMAL_THR
OTTLING_TEMP.CORE
_0
Cycles that the PCU records that core
0 is above the thermal throttling
threshold temperature.
80H 02H UNC_THERMAL_THR
OTTLING_TEMP.CORE
_1
Cycles that the PCU records that core
1 is above the thermal throttling
threshold temperature.
80H 04H UNC_THERMAL_THR
OTTLING_TEMP.CORE
_2
Cycles that the PCU records that core
2 is above the thermal throttling
threshold temperature.
80H 08H UNC_THERMAL_THR
OTTLING_TEMP.CORE
_3
Cycles that the PCU records that core
3 is above the thermal throttling
threshold temperature.
81H 01H UNC_THERMAL_THR
OTTLED_TEMP.CORE
_0
Cycles that the PCU records that core
0 is in the power throttled state due
to core’s temperature being above the
thermal throttling threshold.