Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 276
Documentation Changes
Non-architectural Performance monitoring events that are located in the uncore sub-
system are implementation specific between different platforms using processors based
on Intel microarchitecture (Nehalem). Processors with CPUID signature of
DisplayFamily_DisplayModel 06_1AH, 06_1EH, and 06_1FH support performance events
listed in Table A-3.
Table A-3 Non-Architectural Performance Events In the Processor Uncore for Intel Core
i7 Processor and Intel Xeon Processor 5500 Series
Intel Xeon processors with CPUID signature of DisplayFamily_DisplayModel 06_2EH
have a distinct uncore sub-system that is significantly different from the uncore found in
processors with CPUID signature 06_1AH, 06_1EH, and 06_1FH. Non-architectural
Performance monitoring events for its uncore will be available in future documentation.
...
Table A-4 Non-Architectural Performance Events In Next Generation Processor Core
(Codenamed Westmere)
Event
Num.
Umask
Value
Event Mask
Mnemonic Description Comment
...
Event
Num.
Umask
Value
Event Mask
Mnemonic Description Comment
...
0FH 10H MEM_UNCORE_RETI
RED.LOCAL_DRAM
Load instructions retired with a data
source of local DRAM or locally
homed remote cache HITM (Precise
Event)
...
20H 01H LSD_OVERFLOW Number of loops that can not stream
from the instruction queue.
...
24H 0CH L2_RQSTS.RFOS Counts all L2 store RFO requests. L2
RFO requests include both L1D
demand RFO misses as well as L1D
RFO prefetches..
...
B1H 1FH UOPS_EXECUTED.CO
RE_ACTIVE_CYCLES_
NO_PORT5
Counts number of cycles there are
one or more uops being executed
and were issued on ports 0-4. This is
a core count only and can not be
collected per thread.
...