Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 275
Documentation Changes
Table A-2 Non-Architectural Performance Events In the Processor Core for Intel Core i7
Processor and Intel Xeon Processor 5500 Series
Event
Num.
Umask
Value
Event Mask
Mnemonic Description Comment
04H 07H SB_DRAIN.ANY Counts the number of store buffer
drains.
...
0FH 01H MEM_UNCORE_RETI
RED.L3_DATA_MISS_
UNKNOWN
Counts number of memory load
instructions retired where the
memory reference missed L3 and
data source is unknown.
Available only for
CPUID signature
06_2EH
...
0FH 80H MEM_UNCORE_RETI
RED.UNCACHEABLE
Counts number of memory load
instructions retired where the
memory reference missed the L1,
L2 and L3 caches and to perform I/
O.
Available only for
CPUID signature
06_2EH
...
B1H 1FH UOPS_EXECUTED.CO
RE_ACTIVE_CYCLES_
NO_PORT5
Counts cycles when the Uops
executed were issued from any
ports except port 5. Use Cmask=1
for active cycles; Cmask=0 for
weighted cycles; Use CMask=1,
Invert=1 to count P0-4 stalled
cycles Use Cmask=1, Edge=1,
Invert=1 to count P0-4 stalls.
...
B1H 3FH UOPS_EXECUTED.CO
RE_ACTIVE_CYCLES
Counts cycles when the Uops are
executing . Use Cmask=1 for active
cycles; Cmask=0 for weighted
cycles; Use CMask=1, Invert=1 to
count P0-4 stalled cycles Use
Cmask=1, Edge=1, Invert=1 to
count P0-4 stalls.
...
B7H 01H OFF_CORE_RESPONS
E_0
see Section 30.6.1.3, “Off-core
Response Performance Monitoring
in the Processor Core”
Requires
programming
MSR 01A6H
...
BBH 01H OFF_CORE_RESPONS
E_1
see Section 30.6.1.3, “Off-core
Response Performance Monitoring
in the Processor Core”
Requires
programming
MSR 01A7H
...