Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 272
Documentation Changes
12. Updates to Chapter 30, Volume 3B
Change bars show changes to Chapter 30 of the Intel
®
64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 3B: System Programming Guide, Part 2.
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30.2.3 Pre-defined Architectural Performance Events
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A processor that supports architectural performance monitoring may not support all the
predefined architectural performance events (Table 30-1). The non-zero bits in
CPUID.0AH:EBX indicate the events that are not available.
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30.6 PERFORMANCE MONITORING FOR PROCESSORS BASED
ON INTEL
®
MICROARCHITECTURE (NEHALEM)
Intel Core i7 processor family
1
supports architectural performance monitoring capability
with version ID 3 (see Section 30.2.2.2) and a host of non-architectural monitoring
capabilities. The Intel Core i7 processor family is based on Intel® Microarchitecture
(Nehalem), and provides four general-purpose performance counters (IA32_PMC0,
IA32_PMC1, IA32_PMC2, IA32_PMC3) and three fixed-function performance counters
(IA32_FIXED_CTR0, IA32_FIXED_CTR1, IA32_FIXED_CTR2) in the processor core.
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30.6.1.1 Precise Event Based Sampling (PEBS)
All four general-purpose performance counters, IA32_PMCx, can be used for PEBS if the
performance event supports PEBS. Software uses IA32_MISC_ENABLES[7] and
IA32_MISC_ENABLES[12] to detect whether the performance monitoring facility and
PEBS functionality are supported in the processor. The MSR IA32_PEBS_ENABLE
provides 4 bits that software must use to enable which IA32_PMCx overflow condition
will cause the PEBS record to be captured.
Additionally, the PEBS record is expanded to allow latency information to be captured.
The MSR IA32_PEBS_ENABLE provides 4 additional bits that software must use to
enable latency data recording in the PEBS record upon the respective IA32_PMCx
overflow condition. The layout of IA32_PEBS_ENABLE is shown in Figure 30-13.
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Programming PEBS Facility
Only a subset of non-architectural performance events in the processor support PEBS.
The subset of precise events are listed in Table 30-10. In addition to using
IA32_PERFEVTSELx to specify event unit/mask settings and setting the EN_PMCx bit in
1. Intel Xeon processor 5500 series and 3400 series are also based on Intel microarchitecture
(Nehalem), so the performance monitoring facilities described in this section generally also apply.