Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 268
Documentation Changes
10. Updates to Chapter 25, Volume 3B
Change bars show changes to Chapter 25 of the Intel
®
64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 3B: System Programming Guide, Part 2.
------------------------------------------------------------------------------------------
...
25.2.2 EPT Translation Mechanism
...
Because a PDPTE is identified using bits 47:30 of the guest-physical address, it controls
access to a 1-GByte region of the guest-physical-address space. Use of the PDPTE
depends on the value of bit 7 in that entry:
1
• If bit 7 of the EPT PDPTE is 1, the EPT PDPTE maps a 1-GByte page (see Table 25-2).
The final physical address is computed as follows:
1. Not all processors allow bit 7 of an EPT PDPTE to be set to 1. Software should read the VMX capabil-
ity MSR IA32_VMX_EPT_VPID_CAP (see Appendix G.10) to determine whether this is allowed.
Table 25-2 Format of an EPT Page-Directory-Pointer-Table Entry (PDPTE) that Maps a 1-
GByte Page
Bit
Position(s)
Contents
0 Read access; indicates whether reads are allowed from the 1-GByte page
referenced by this entry
1 Write access; indicates whether writes are allowed to the 1-GByte page
referenced by this entry
2 Execute access; indicates whether instruction fetches are allowed from the 1-
GByte page referenced by this entry
5:3 EPT memory type for this 1-GByte page (see Section 25.2.4)
6 Ignore PAT memory type for this 1-GByte page (see Section 25.2.4)
7 Must be 1 (otherwise, this entry references an EPT page directory)
11:8 Ignored
29:12 Reserved (must be 0)
(N–1):30 Physical address of the 1-GByte page referenced by this entry
1
NOTES:
1. N is the physical-address width supported by the logical processor.
51:N Reserved (must be 0)
63:52 Ignored