Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 258
Documentation Changes
10.12.9 ICR Operation in x2APIC Mode
In x2APIC mode, the layout of the Interrupt Command Register is shown in Figure
10-12. The lower 32 bits of ICR in x2APIC mode is identical to the lower half of the ICR
in xAPIC mode, except the Delivery Status bit is removed since it is not needed in x2APIC
mode. The destination ID field is expanded to 32 bits in x2APIC mode.
To send an IPI using the ICR, software must set up the ICR to indicate the type of IPI
message to be sent and the destination processor or processors. Self IPIs can also be
sent using the SELF IPI register (see Section 10.12.11).
A single MSR write to the Interrupt Command Register is required for dispatching an
interrupt in x2APIC mode. With the removal of the Delivery Status bit, system software
no longer has a reason to read the ICR. It remains readable only to aid in debugging;
however, software should not assume the value returned by reading the ICR is the last
written value
A destination ID value of FFFF_FFFFH is used for broadcast of interrupts in both logical
destination and physical destination modes.
Figure 10-29. Interrupt Command Register (ICR) in x2APIC Mode
31 0
Reserved
7
Vector
Destination Shorthand
810
Delivery Mode
000: Fixed
001: Reserved
00: No Shorthand
01: Self
111213141516171819
10: All Including Self
11: All Excluding Self
010: SMI
011: Reserved
100: NMI
101: INIT
110: Start Up
111: Reserved
Destination Mode
0: Physical
1: Logical
Level
0 = De-assert
1 = Assert
Trigger Mode
0: Edge
1: Level
63
32
Destination Field
Address: 830H (63 - 0)
Value after Reset: 0H
Reserved
20