Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 257
Documentation Changes
enumerating topology. The presence of CPUID leaf 0BH in a processor does not guar-
antee support for x2APIC. If CPUID.EAX=0BH, ECX=0H:EBX returns zero and maximum
input value for basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
supported on that processor.
The extended topology enumeration leaf is intended to assist software with enumerating
processor topology on systems that requires 32-bit x2APIC IDs to address individual
logical processors. Details of CPUID leaf 0BH can be found in the reference pages of
CPUID in Chapter 3 of Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 2A.
Processor topology enumeration algorithm for processors supporting the extended
topology enumeration leaf of CPUID and processors that do not support CPUID leaf 0BH
are treated in Section 8.9.4, “Algorithm for Three-Level Mappings of APIC_ID”.
...
10.12.8 Error Handling in x2APIC Mode
RDMSR and WRMSR operations to reserved addresses in x2APIC mode cause general-
protection exceptions, as do reserved-bit violations (see Section 10.12.1.3). Beyond
illegal register access and reserved bit violations, other APIC errors are logged in Error
Status Register. Writes of a non-zero value to the Error Status Register in x2APIC mode
cause general-protection exceptions. Figure 10-28 illustrates the Error Status Register in
x2APIC mode.
Write to the ICR (in xAPIC and x2APIC modes) or to SELF IPI register (x2APIC mode
only) with an illegal vector (vector ≤ 0FH) will set the “Send Illegal Vector” bit.
On receiving an IPI with an illegal vector (vector ≤ 0FH), the “Receive Illegal Vector” bit
will be set. On receiving an interrupt with illegal vector in the range 0H – 0FH, the inter-
rupt will not be delivered to the processor nor will an IRR bit be set in that range. Only
the ESR “Receive Illegal Vector” bit will be set.
If the ICR is programmed with lowest priority delivery mode then the “Re-directible IPI”
bit will be set in x2APIC modes (same as legacy xAPIC behavior) and the interrupt will
not be processed.
Write to the ICR with both lowest priority delivery mode and illegal vector, will set the
“re-directible IPI” error bit. The interrupt will not be processed and hence the “Send
Illegal Vector” error bit will not be set.
Figure 10-28 Error Status Register (ESR) in x2APIC Mode
MSR Address: 828H
31
0
Reserved
78123456
Illegal Register Address
Received Illegal Vector
Send Illegal Vector
Redirectible IPI
Reserved