Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 256
Documentation Changes
10.12.5 x2APIC State Transitions
This section provides a detailed description of the x2APIC states of a local x2APIC unit,
transitions between these states as well as interactions of these states with INIT and
RESET.
10.12.5.1 x2APIC States
The valid states for a local x2APIC unit is listed in Table 10-5:
• APIC disabled: IA32_APIC_BASE[EN]=0 and IA32_APIC_BASE[EXTD]=0
• xAPIC mode: IA32_APIC_BASE[EN]=1 and IA32_APIC_BASE[EXTD]=0
• x2APIC mode: IA32_APIC_BASE[EN]=1 and IA32_APIC_BASE[EXTD]=1
• Invalid: IA32_APIC_BASE[EN]=0 and IA32_APIC_BASE[EXTD]=1
The state corresponding to EXTD=1 and EN=0 is not valid and it is not possible to get
into this state. An execution of WRMSR to the IA32_APIC_BASE_MSR that attempts a
transition from a valid state to this invalid state causes a general-protection exception.
Figure 10-27 shows the comprehensive state transition diagram for a local x2APIC unit.
...
x2APIC Transitions From x2APIC Mode
From the x2APIC mode, the only valid x2APIC transition using IA32_APIC_BASE is to the
state where the x2APIC is disabled by setting EN to 0 and EXTD to 0. The x2APIC ID (32
bits) and the legacy local xAPIC ID (8 bits) are preserved across this transition. A transi-
tion from the x2APIC mode to xAPIC mode is not valid, and the corresponding WRMSR to
the IA32_APIC_BASE MSR causes a general-protection exception.
A RESET in this state places the x2APIC in xAPIC mode. All APIC registers (including the
local APIC ID register) are initialized as described in Section 10.12.5.1.
An INIT in this state keeps the x2APIC in the x2APIC mode. The state of the local APIC
ID register is preserved (all 32 bits). However, all the other APIC registers are initialized
as a result of the INIT transition.
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10.12.7 CPUID Extensions And Topology Enumeration
For Intel 64 and IA-32 processors that support x2APIC, a value of 1 reported by
CPUID.01H:ECX[21] indicates that the processor supports x2APIC and the extended
topology enumeration leaf (CPUID.0BH).
The extended topology enumeration leaf can be accessed by executing CPUID with EAX
= 0BH. Processors that do not support x2APIC may support CPUID leaf 0BH. Software
can detect the availability of the extended topology enumeration leaf (0BH) by
performing two steps:
• Check maximum input value for basic CPUID information by executing CPUID with
EAX= 0. If CPUID.0H:EAX is greater than or equal or 11 (0BH), then proceed to next
step
• Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero.
If both of the above conditions are true, extended topology enumeration leaf is available.
If available, the extended topology enumeration leaf is the preferred mechanism for