Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 253
Documentation Changes
815H 150H ISR bits 191:160 Read-only
816H 160H ISR bits 223:192 Read-only
817H 170H ISR bits 255:224 Read-only
818H 180H Trigger Mode Register
(TMR); bits 31:0
Read-only
819H 190H TMR bits 63:32 Read-only
81AH 1A0H TMR bits 95:64 Read-only
81BH 1B0H TMR bits 127:96 Read-only
81CH 1C0H TMR bits 159:128 Read-only
81DH 1D0H TMR bits 191:160 Read-only
81EH 1E0H TMR bits 223:192 Read-only
81FH 1F0H TMR bits 255:224 Read-only
820H 200H Interrupt Request
Register (IRR); bits
31:0
Read-only
821H 210H IRR bits 63:32 Read-only
822H 220H IRR bits 95:64 Read-only
823H 230H IRR bits 127:96 Read-only
824H 240H IRR bits 159:128 Read-only
825H 250H IRR bits 191:160 Read-only
826H 260H IRR bits 223:192 Read-only
827H 270H IRR bits 255:224 Read-only
828H 280H Error Status Register
(ESR)
Read/write WRMSR of a non-zero
value causes #GP(0). See
Section 10.5.3 and
Section 10.12.8.
82FH 2F0H LVT CMCI register Read/write See Figure 15-10 for
reserved bits.
830H
4
300H and
310H
Interrupt Command
Register (ICR)
Read/write See Figure 10-29 for
reserved bits
832H 320H LVT Timer register Read/write See Figure 10-8 for
reserved bits.
833H 330H LVT Thermal Sensor
register
Read/write See Figure 10-8 for
reserved bits.
834H 340H LVT Performance
Monitoring register
Read/write See Figure 10-8 for
reserved bits.
835H 350H LVT LINT0 register Read/write See Figure 10-8 for
reserved bits.
836H 360H LVT LINT1 register Read/write See Figure 10-8 for
reserved bits.
MSR Address
(x2APIC mode)
MMIO Offset
(xAPIC mode)
Register Name
MSR R/W
Semantics
Comments