Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 252
Documentation Changes
each register is available on the page referenced by IA32_APIC_BASE[35:12] in xAPIC
mode.
There is a one-to-one mapping between the x2APIC MSRs and the legacy xAPIC register
offsets with the following exceptions:
• The Destination Format Register (DFR): The DFR, supported at offset 0E0H in
x2APIC mode, is not supported in x2APIC mode. There is no MSR with address 80EH.
• The Interrupt Command Register (ICR): The two 32-bit registers in xAPIC mode (at
offsets 300H and 310H) are merged into a single 64-bit MSR in x2APIC mode (with
MSR address 830H). There is no MSR with address 831H.
• The SELF IPI register. This register is available only in x2APIC mode at address 83FH.
In xAPIC mode, there is no register defined at offset 3F0H.
Addresses in the range 800H–BFFH that are not listed in Table 10-6 (including 80EH and
831H) are reserved. Executions of RDMSR and WRMSR that attempt to access such
addresses cause general-protection exceptions.
The MSR address space is compressed to allow for future growth. Every 32 bit register
on a 128-bit boundary in the legacy MMIO space is mapped to a single MSR in the local
x2APIC MSR address space. The upper 32-bits of all x2APIC MSRs (except for the ICR)
are reserved.
Table 10-6 Local APIC Register Address Map Supported by x2APIC
MSR Address
(x2APIC mode)
MMIO Offset
(xAPIC mode)
Register Name
MSR R/W
Semantics
Comments
802H 020H Local APIC ID register Read-only
1
See Section 10.12.5.1 for
initial values.
803H 030H Local APIC Version
register
Read-only Same version used in
xAPIC mode and x2APIC
mode.
808H 080H Task Priority Register
(TPR)
Read/write Bits 31:8 are reserved.
2
80AH 0A0H Processor Priority
Register (PPR)
Read-only
80BH 0B0H EOI register Write-
only
3
WRMSR of a non-zero
value causes #GP(0).
80DH 0D0H Logical Destination
Register (LDR)
Read-only Read/write in xAPIC
mode.
80FH 0F0H Spurious Interrupt
Vector Register (SVR)
Read/write See Section 10.9 for
reserved bits.
810H 100H In-Service Register
(ISR); bits 31:0
Read-only
811H 110H ISR bits 63:32 Read-only
812H 120H ISR bits 95:64 Read-only
813H 130H ISR bits 127:96 Read-only
814H 140H ISR bits 159:128 Read-only