Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 251
Documentation Changes
• Uses MSR programming interface to access APIC registers in x2APIC mode instead of
memory-mapped interfaces. Memory-mapped interface is supported when operating
in xAPIC mode.
10.12.1 Detecting and Enabling x2APIC Mode
Processor support for x2APIC mode can be detected by executing CPUID with EAX=1 and
then checking ECX, bit 21 ECX. If CPUID.(EAX=1):ECX.21 is set , the processor supports
the x2APIC capability and can be placed into the x2APIC mode.
System software can place the local APIC in the x2APIC mode by setting the x2APIC
mode enable bit (bit 10) in the IA32_APIC_BASE MSR at MSR address 01BH. The layout
for the IA32_APIC_BASE MSR is shown in Figure 10-26.
Table 10-5, “x2APIC operating mode configurations” describe the possible combinations
of the enable bit (EN - bit 11) and the extended mode bit (EXTD - bit 10) in the
IA32_APIC_BASE MSR.
Table 10-5 x2APIC Operating Mode Configurations
Once the local APIC has been switched to x2APIC mode (EN = 1, EXTD = 1), switching
back to xAPIC mode would require system software to disable the local APIC unit. Specif-
ically, attempting to write a value to the IA32_APIC_BASE MSR that has (EN= 1, EXTD =
0) when the local APIC is enabled and in x2APIC mode causes a general-protection
exception. Once bit 10 in IA32_APIC_BASE MSR is set, the only way to leave x2APIC
mode using IA32_APIC_BASE would require a WRMSR to set both bit 11 and bit 10 to
zero. Section 10.12.5, “x2APIC State Transitions” provides a detailed state diagram for
the state transitions allowed for the local APIC.
...
The MSR address range 800H through BFFH is architecturally reserved and dedicated for
accessing APIC registers in x2APIC mode. Table 10-6 lists the APIC registers that are
available in x2APIC mode. When appropriate, the table also gives the offset at which
Figure 10-26 IA32_APIC_BASE MSR Supporting x2APIC
xAPIC global enable
(IA32_APIC_BASE[11])
x2APIC enable
(IA32_APIC_BASE[10]) Description
0 0 local APIC is disabled
01Invalid
1 0 local APIC is enabled in xAPIC mode
1 1 local APIC is enabled in x2APIC mode
BSP—Processor is BSP
EN—xAPIC global enable/disable
APIC Base—Base physical address
63 071011 8912
Reserved
36 35
APIC Base
Reserved
EXTD—Enable x2APIC mode