Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 249
Documentation Changes
priority level is established when the MOV CR8 instruction completes execution. Soft-
ware does not need to force serialization after loading the TPR using MOV CR8.
Use of the MOV CRn instruction requires a privilege level of 0. Programs running at priv-
ilege level greater than 0 cannot read or write the TPR. An attempt to do so causes a
general-protection exception. The TPR is abstracted from the interrupt controller (IC),
which prioritizes and manages external interrupt delivery to the processor. The IC can be
an external device, such as an APIC or 8259. Typically, the IC provides a priority mecha-
nism similar or identical to the TPR. The IC, however, is considered implementation-
dependent with the under-lying priority mechanisms subject to change. CR8, by
contrast, is part of the Intel 64 architecture. Software can depend on this definition
remaining unchanged.
Figure 10-22 shows the layout of CR8; only the low four bits are used. The remaining 60
bits are reserved and must be written with zeros. Failure to do this causes a general-
protection exception.
...
10.9 SPURIOUS INTERRUPT
A special situation may occur when a processor raises its task priority to be greater than
or equal to the level of the interrupt for which the processor INTR signal is currently
being asserted. If at the time the INTA cycle is issued, the interrupt that was to be
dispensed has become masked (programmed by software), the local APIC will deliver a
spurious-interrupt vector. Dispensing the spurious-interrupt vector does not affect the
ISR, so the handler for this vector should return without an EOI.
The vector number for the spurious-interrupt vector is specified in the spurious-interrupt
vector register (see Figure 10-23). The functions of the fields in this register are as
follows:
Spurious Vector Determines the vector number to be delivered to the processor
when the local APIC generates a spurious vector.
(Pentium 4 and Intel Xeon processors.) Bits 0 through 7 of the this
field are programmable by software.
(P6 family and Pentium processors). Bits 4 through 7 of the this field
are programmable by software, and bits 0 through 3 are hardwired
to logical ones. Software writes to bits 0 through 3 have no effect.
APIC Software Enable/Disable
Allows software to temporarily enable (1) or disable (0) the local
APIC (see Section 10.4.3, “Enabling or Disabling the Local APIC”).
Focus Processor Checking
Determines if focus processor checking is enabled (0) or disabled
(1) when using the lowest-priority delivery mode. In Pentium 4 and
Intel Xeon processors, this bit is reserved and should be cleared to
0.
Suppress EOI Broadcasts
Determines whether an EOI for a level-triggered interrupt causes
EOI messages to be broadcast to the I/O APICs (0) or not (1). See
Section 10.8.5. The default value for this bit is 0, indicating that EOI
broadcasts are performed. This bit is reserved to 0 if the processor
does not support EOI-broadcast suppression.