Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 248
Documentation Changes
Upon receiving and EOI, the APIC clears the highest priority bit in the ISR and dispatches
the next highest priority interrupt to the processor. If the terminated interrupt was a
level-triggered interrupt, the local APIC also sends an end-of-interrupt message to all I/
O APICs.
System software may prefer to direct EOIs to specific I/O APICs rather than having the
local APIC send end-of-interrupt messages to all I/O APICs.
Software can inhibit the broadcast of EOI message by setting bit 12 of the Spurious
Interrupt Vector Register (see Section 10.9). If this bit is set, a broadcast EOI is not
generated on an EOI cycle even if the associated TMR bit indicates that the current inter-
rupt was level-triggered. The default value for the bit is 0, indicating that EOI broadcasts
are performed.
Bit 12 of the Spurious Interrupt Vector Register is reserved to 0 if the processor does not
support suppression of EOI broadcasts. Support for EOI-broadcast suppression is
reported in bit 24 in the Local APIC Version Register (see Section 10.4.8); the feature is
supported if that bit is set to 1. When supported, the feature is available in both xAPIC
mode and x2APIC mode.
System software desiring to perform directed EOIs for level-triggered interrupts should
set bit 12 of the Spurious Interrupt Vector Register and follow each the EOI to the local
xAPIC for a level triggered interrupt with a directed EOI to the I/O APIC generating the
interrupt (this is done by writing to the I/O APIC’s EOI register). System software
performing directed EOIs must retain a mapping associating level-triggered interrupts
with the I/O APICs in the system.
...
10.8.6 Task Priority in IA-32e Mode
In IA-32e mode, operating systems can manage the 16 priority classes of external inter-
rupts (see Section 10.8.3, “Interrupt, Task, and Processor Priority”) explicitly using the
task priority register (TPR). Operating systems can use the TPR to temporarily block
specific (low-priority) interrupts from interrupting a high-priority task. This is done by
loading TPR with a value corresponding to the highest-priority interrupt that is to be
blocked. For example:
• Loading the TPR with a value of 8 (01000B) blocks all interrupts with a priority of 8
or less while allowing all interrupts with a priority of nine or more to be recognized.
• Loading the TPR with zero enables all external interrupts.
• Loading the TPR with 0F (01111B) disables all external interrupts.
The TPR (shown in Figure 10-18) is cleared to 0 on reset. In 64-bit mode, software can
read and write the TPR using an alternate interface, MOV CR8 instruction. The new
Figure 10-21 EOI Register
31
0
Address: 0FEE0 00B0H
Value after reset: 0H