Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 247
Documentation Changes
— Destination Mode — Selects one of two destination modes (physical or logical).
— Destination Field — In physical destination mode, used to specify the APIC ID
of the destination processor; in logical destination mode, used to specify a
message destination address (MDA) that can be used to select specific
processors in clusters.
— Destination Shorthand — A quick method of specifying all processors, all
excluding self, or self as the destination.
— Delivery mode, Lowest Priority — Architecturally specifies that a lowest-
priority arbitration mechanism be used to select a destination processor from a
specified group of processors. The ability of a processor to send a lowest priority
IPI is model specific and should be avoided by BIOS and operating system
software.
• Local destination register (LDR) — Used in conjunction with the logical
destination mode and MDAs to select the destination processors.
• Destination format register (DFR) — Used in conjunction with the logical
destination mode and MDAs to select the destination processors.
How the ICR, LDR, and DFR are used to select an IPI destination depends on the desti-
nation mode used: physical, logical, broadcast/self, or lowest-priority delivery mode.
These destination modes are described in the following sections.
Determination of IPI destinations in x2APIC mode is discussed in Section 10.12.10.
...
NOTES
All processors that have their APIC software enabled (using the spurious
vector enable/disable bit) must have their DFRs (Destination Format
Registers) programmed identically.
The default mode for DFR is flat mode. If you are using cluster mode,
DFRs must be programmed before the APIC is software enabled. Since
some chipsets do not accurately track a system view of the logical mode,
program DFRs as soon as possible after starting the processor.
10.6.2.3 Broadcast/Self Delivery Mode
The destination shorthand field of the ICR allows the delivery mode to be by-passed in
favor of broadcasting the IPI to all the processors on the system bus and/or back to itself
(see Section 10.6.1, “Interrupt Command Register (ICR)”). Three destination short-
hands are supported: self, all excluding self, and all including self. The destination mode
is ignored when a destination shorthand is used.
...
10.8.5 Signaling Interrupt Servicing Completion
For all interrupts except those delivered with the NMI, SMI, INIT, ExtINT, the start-up, or
INIT-Deassert delivery mode, the interrupt handler must include a write to the end-of-
interrupt (EOI) register (see Figure 10-21). This write must occur at the end of the
handler routine, sometime before the IRET instruction. This action indicates that the
servicing of the current interrupt is complete and the local APIC can issue the next inter-
rupt from the ISR.