Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 246
Documentation Changes
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10.6.1 Interrupt Command Register (ICR)
The interrupt command register (ICR) is a 64-bit local APIC register (see Figure 10-12)
that allows software running on the processor to specify and send interprocessor inter-
rupts (IPIs) to other processors in the system.
To send an IPI, software must set up the ICR to indicate the type of IPI message to be
sent and the destination processor or processors. (All fields of the ICR are read-write by
software with the exception of the delivery status field, which is read-only.) The act of
writing to the low doubleword of the ICR causes the IPI to be sent.
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Delivery Status (Read Only)
Indicates the IPI delivery status, as follows:
0 (Idle) Indicates that this local APIC has completed
sending any previous IPIs.
1 (Send Pending)
Indicates that this local APIC has not completed
sending the last IPI.
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Destination Specifies the target processor or processors. This field is only used
when the destination shorthand field is set to 00B. If the destination
mode is set to physical, then bits 56 through 59 contain the APIC ID
of the target processor for Pentium and P6 family processors and
bits 56 through 63 contain the APIC ID of the target processor the
for Pentium 4 and Intel Xeon processors. If the destination mode is
set to logical, the interpretation of the 8-bit destination field
depends on the settings of the DFR and LDR registers of the local
APICs in all the processors in the system (see Section 10.6.2,
“Determining IPI Destination”).
Not all combinations of options for the ICR are valid. Table 10-3 shows the valid combi-
nations for the fields in the ICR for the Pentium 4 and Intel Xeon processors; Table 10-4
shows the valid combinations for the fields in the ICR for the P6 family processors. Also
note that the lower half of the ICR may not be preserved over transitions to the deepest
C-States.
ICR operation in x2APIC mode is discussed in Section 10.12.9.
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10.6.2 Determining IPI Destination
The destination of an IPI can be one, all, or a subset (group) of the processors on the
system bus. The sender of the IPI specifies the destination of an IPI with the following
APIC registers and fields within the registers:
• ICR Register — The following fields in the ICR register are used to specify the
destination of an IPI: