Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 245
Documentation Changes
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10.5.4 APIC Timer
The local APIC unit contains a 32-bit programmable timer that is available to software to
time events or operations. This timer is set up by programming four registers: the divide
configuration register (see Figure 10-10), the initial-count and current-count registers
(see Figure 10-11), and the LVT timer register (see Figure 10-8).
If CPUID.06H:EAX.ARAT[bit 2] = 1, the processor’s APIC timer runs at a constant rate
regardless of P-state transitions and it continues to run at the same rate in deep C-
states.
If CPUID.06H:EAX.ARAT[bit 2] = 0 or if CPUID 06H is not supported, the APIC timer may
temporarily stop while the processor is in deep C-states or during transitions caused by
Enhanced Intel SpeedStep® Technology.
Send Illegal Vector Set when the local APIC detects an illegal vector in the message that
it is sending.
Receive Illegal Vector Set when the local APIC detects an illegal vector in the message it
received, including an illegal vector code in the local vector table
interrupts or in a self-interrupt.
Illegal Reg. Address (Intel Core, Intel Atom, Pentium 4, Intel Xeon, and P6 family
processors only) Set when the processor is trying to access a
register in the processor's local APIC register address space that is
reserved (see Table 10-1). Addresses in one of the 0x10 byte
regions marked reserved are illegal register addresses.
The Local APIC Register Map is the address range of the APIC
register base address (specified in the IA32_APIC_BASE MSR) plus
4KBytes.
Figure 10-10 Divide Configuration Register
Table 10-2. ESR Flags
FLAG Function
Send Checksum Error (P6 family and Pentium processors only) Set when the local APIC
detects a checksum error for a message that it sent on the APIC bus.
Receive Checksum Error (P6 family and Pentium processors only) Set when the local APIC
detects a checksum error for a message that it received on the APIC
bus.
Address: FEE0 03E0H
Value after reset: 0H
0
Divide Value (bits 0, 1 and 3)
000: Divide by 2
001: Divide by 4
010: Divide by 8
011: Divide by 16
100: Divide by 32
101: Divide by 64
110: Divide by 128
111: Divide by 1
31
0
Reserved
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