Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 244
Documentation Changes
when the local APIC sets one of the error bits in the ESR. The LVT error register allows
selection of the interrupt vector to be delivered to the processor core when APIC error is
detected. The LVT error register also provides a means of masking an APIC error inter-
rupt.
The ESR is a write/read register. A write (of any value) to the ESR must be done to
update the register before attempting to read it. This write clears any previously logged
errors and updates the ESR with any errors detected since the last write to the ESR.
Errors are collected regardless of LVT Error mask bit, but the APIC will only issue an
interrupt due to the error if the LVT Error mask bit is cleared.
The functions of the ESR are listed in Table 10-2.
Error handling in x2APIC mode is discussed in Section 10.12.8.
Figure 10-9 Error Status Register (ESR)
Table 10-2. ESR Flags
FLAG Function
Send Checksum Error (P6 family and Pentium processors only) Set when the local APIC
detects a checksum error for a message that it sent on the APIC bus.
Receive Checksum Error (P6 family and Pentium processors only) Set when the local APIC
detects a checksum error for a message that it received on the APIC
bus.
Send Accept Error (P6 family and Pentium processors only) Set when the local APIC
detects that a message it sent was not accepted by any APIC on the
APIC bus.
Receive Accept Error (P6 family and Pentium processors only) Set when the local APIC
detects that the message it received was not accepted by any APIC
on the APIC bus, including itself.
Address: FEE0 0280H
Value after reset: 0H
31
0
Reserved
78123456
Illegal Register Address
1
Received Illegal Vector
Send Illegal Vector
Reserved
Receive Accept Error
2
Send Accept Error
2
Receive Checksum Error
2
Send Checksum Error
2
2. Only used in the P6 family and Pentium processors;
reserved in Intel Core, Pentium 4 and Intel Xeon processors.
1. Used in Intel Core, Pentium 4, Intel Xeon, and P6 family
processors; reserved in the Pentium processor.
NOTES: