Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 242
Documentation Changes
Suppress EOI-broadcasts
Indicates whether software can inhibit the broadcast of EOI
message by setting bit 12 of the Spurious Interrupt Vector Register;
see Section 10.8.5 and Section 10.9.
...
10.5.1 Local Vector Table
The local vector table (LVT) allows software to specify the manner in which the local
interrupts are delivered to the processor core. It consists of the following 32-bit APIC
registers (see Figure 10-8), one for each local interrupt:
• LVT Timer Register (FEE0 0320H) — Specifies interrupt delivery when the APIC
timer signals an interrupt (see Section 10.5.4, “APIC Timer”).
• LVT Thermal Monitor Register (FEE0 0330H) — Specifies interrupt delivery
when the thermal sensor generates an interrupt (see Section 14.5.2, “Thermal
Monitor”). This LVT entry is implementation specific, not architectural. If imple-
mented, it will always be at base address FEE0 0330H.
• LVT Performance Counter Register (FEE0 0340H) — Specifies interrupt
delivery when a performance counter generates an interrupt on overflow (see
Section 30.8.5.8, “Generating an Interrupt on Overflow”). This LVT entry is imple-
mentation specific, not architectural. If implemented, it is not guaranteed to be at
base address FEE0 0340H.
• LVT LINT0 Register (FEE0 0350H) — Specifies interrupt delivery when an
interrupt is signaled at the LINT0 pin.
• LVT LINT1 Register (FEE0 0360H) — Specifies interrupt delivery when an
interrupt is signaled at the LINT1 pin.
• LVT Error Register (FEE0 0370H) — Specifies interrupt delivery when the APIC
detects an internal error (see Section 10.5.3, “Error Handling”).
• CMCI LVT Register (FEE0 02F0H) — Specifies interrupt delivery when an overflow
condition of corrected machine check error count reaching a threshold value
occurred in a machine check bank supporting CMCI (see Section 15.5.1, “CMCI Local
APIC Interface”).
The LVT performance counter register and its associated interrupt were introduced in the
P6 processors and are also present in the Pentium 4 and Intel Xeon processors. The LVT
Figure 10-7. Local APIC Version Register
31
0
Reserved
7823 15
Support for EOI-broadcast suppression
16
Reserved
25 24
VersionMax LVT Entry
Value after reset: 00BN 00VVH
V = Version, N = # of LVT entries minus 1,
Address: FEE0 0030H
B = 1 if EOI-broadcast suppression supported