Specifications

Intel
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64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 239
Documentation Changes
6. Updates to Chapter 10, Volume 3A
Change bars show changes to Chapter 10 of the Intel
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64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 3A: System Programming Guide, Part 1.
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10.3 THE INTEL
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82489DX EXTERNAL APIC, THE APIC, THE
XAPIC, AND THE X2APIC
The local APIC in the P6 family and Pentium processors is an architectural subset of the
Intel
®
82489DX external APIC. See Section 19.27.1, “Software Visible Differences
Between the Local APIC and the 82489DX.”
The APIC architecture used in the Pentium 4 and Intel Xeon processors (called the xAPIC
architecture) is an extension of the APIC architecture found in the P6 family processors.
The primary difference between the APIC and xAPIC architectures is that with the xAPIC
architecture, the local APICs and the I/O APIC communicate through the system bus.
With the APIC architecture, they communication through the APIC bus (see Section
10.2, “System Bus Vs. APIC Bus”). Also, some APIC architectural features have been
extended and/or modified in the xAPIC architecture. These extensions and modifications
are described in Section 10.4 through Section 10.10.
The x2APIC architecture is an extension of the xAPIC architecture, primarily to increase
processor addressability. The x2APIC architecture provides backward compatibility to
the xAPIC architecture and forward extendability for future Intel platform innovations.
These extensions and modifications are supported by a new mode of execution (x2APIC
mode) are detailed in Section 10.12.
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10.4.1 The Local APIC Block Diagram
Figure 10-4 gives a functional block diagram for the local APIC. Software interacts with
the local APIC by reading and writing its registers. APIC registers are memory-mapped
to a 4-KByte region of the processor’s physical address space with an initial starting
address of FEE00000H. For correct APIC operation, this address space must be mapped
to an area of memory that has been designated as strong uncacheable (UC). See Section
11.3, “Methods of Caching Available.”
In MP system configurations, the APIC registers for Intel 64 or IA-32 processors on the
system bus are initially mapped to the same 4-KByte region of the physical address
space. Software has the option of changing initial mapping to a different 4-KByte region
for all the local APICs or of mapping the APIC registers for each local APIC to its own
4-KByte region. Section 10.4.5, “Relocating the Local APIC Registers,” describes how to
relocate the base address for APIC registers.
On processors supporting x2APIC architecture (indicated by CPUID.01H:ECX[21] = 1),
the local APIC supports operation in the xAPIC mode (as described in Section 10.4. Addi-
tionally, software can enable the local APIC to operate in x2APIC mode for extended
processor addressability (see Section 10.12).
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