Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 238
Documentation Changes
1. Waits on the BIOS initialization Lock Semaphore. When control of the semaphore is
attained, initialization continues.
2. Loads the microcode update into the processor.
3. Initializes the MTRRs (using the same mapping that was used for the BSP).
4. Enables the cache.
5. Executes the CPUID instruction with a value of 0H in the EAX register, then reads the
EBX, ECX, and EDX registers to determine if the AP is “GenuineIntel.”
6. Executes the CPUID instruction with a value of 1H in the EAX register, then saves the
values in the EAX, ECX, and EDX registers in a system configuration space in RAM for
use later.
7. Switches to protected mode and ensures that the APIC address space is mapped to
the strong uncacheable (UC) memory type.
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8.7.11 MICROCODE UPDATE Resources
In an Intel processor supporting Intel Hyper-Threading Technology, the microcode
update facilities are shared between the logical processors; either logical processor can
initiate an update. Each logical processor has its own BIOS signature MSR
(IA32_BIOS_SIGN_ID at MSR address 8BH). When a logical processor performs an
update for the physical processor, the IA32_BIOS_SIGN_ID MSRs for resident logical
processors are updated with identical information. If logical processors initiate an update
simultaneously, the processor core provides the necessary synchronization needed to
ensure that only one update is performed at a time.
Operating system microcode update drivers that adhere to Intel’s guidelines do not need
to be modified to run on processors supporting Intel Hyper-Threading Technology.
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