Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 237
Documentation Changes
• Privileged serializing instructions — INVD, INVEPT, INVLPG, INVVPID, LGDT,
LIDT, LLDT, LTR, MOV (to control register, with the exception of MOV CR8
1
), MOV (to
debug register), WBINVD, and WRMSR.
• Non-privileged serializing instructions — CPUID, IRET, and RSM.
When the processor serializes instruction execution, it ensures that all pending memory
transactions are completed (including writes stored in its store buffer) before it executes
the next
instruction. Nothing can pass a serializing instruction and a serializing instruc-
tion cannot pass any other instruction (read, write, instruction fetch, or I/O). For
example, CPUID can be executed at any privilege level to serialize instruction execution
with no effect on program flow, except that the EAX, EBX, ECX, and EDX registers are
modified.
The following instructions are memory-ordering instructions, not serializing instructions.
These drain the data memory subsystem. They do not serialize the instruction execution
stream:
2
...
8.4.4.1 Typical BSP Initialization Sequence
After the BSP and APs have been selected (by means of a hardware protocol, see Section
8.4.3, “MP Initialization Protocol Algorithm for Intel Xeon Processors”), the BSP begins
executing BIOS boot-strap code (POST) at the normal IA-32 architecture starting
address (FFFF FFF0H). The boot-strap code typically performs the following operations:
1. Initializes memory.
2. Loads the microcode update into the processor.
3. Initializes the MTRRs.
4. Enables the caches.
5. Executes the CPUID instruction with a value of 0H in the EAX register, then reads the
EBX, ECX, and EDX registers to determine if the BSP is “GenuineIntel.”
6. Executes the CPUID instruction with a value of 1H in the EAX register, then saves the
values in the EAX, ECX, and EDX registers in a system configuration space in RAM for
use later.
7. Loads start-up code for the AP to execute into a 4-KByte page in the lower 1 MByte
of memory.
8. Switches to protected mode and ensures that the APIC address space is mapped to
the strong uncacheable (UC) memory type.
...
8.4.4.2 Typical AP Initialization Sequence
When an AP receives the SIPI, it begins executing BIOS AP initialization code at the
vector encoded in the SIPI. The AP initialization code typically performs the following
operations:
1. MOV CR8 is not defined architecturally as a serializing instruction.
2. LFENCE does provide some guarantees on instruction ordering. It does not execute until all prior
instructions have completed locally, and no later instruction begins execution until LFENCE com-
pletes.