Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 234
Documentation Changes
• LFENCE instructions cannot pass earlier reads.
• SFENCE instructions cannot pass earlier writes.
• MFENCE instructions cannot pass earlier reads or writes.
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8.2.4.2 Examples Illustrating Memory-Ordering Principles for String
Operations
The following examples uses the same notation and convention as described in Section
8.2.3.1.
In Example 8-11, processor 0 does one round of (128 iterations) doubleword string store
operation via rep:stosd, writing the value 1 (value in EAX) into a block of 512 bytes from
location _x (kept in ES:EDI) in ascending order. Since each operation stores a double-
word (4 bytes), the operation is repeated 128 times (value in ECX). The block of memory
initially contained 0. Processor 1 is reading two memory locations that are part of the
memory block being updated by processor 0, i.e, reading locations in the range _x to
(_x+511).
It is possible for processor 1 to perceive that the repeated string stores in processor 0
are happening out of order. Assume that fast string operations are enabled on processor
0.
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8.2.5 Strengthening or Weakening the Memory-Ordering Model
The Intel 64 and IA-32 architectures provide several mechanisms for strengthening or
weakening the memory-ordering model to handle special programming situations.
These mechanisms include:
• The I/O instructions, locking instructions, the LOCK prefix, and serializing instruc-
tions force stronger ordering on the processor.
• The SFENCE instruction (introduced to the IA-32 architecture in the Pentium III
processor) and the LFENCE and MFENCE instructions (introduced in the Pentium 4
processor) provide memory-ordering and serialization capabilities for specific types
of memory operations.
• The memory type range registers (MTRRs) can be used to strengthen or weaken
memory ordering for specific area of physical memory (see Section 11.11, “Memory
Type Range Registers (MTRRs)”). MTRRs are available only in the Pentium 4, Intel
Xeon, and P6 family processors.
Example 8-11 Stores Within a String Operation May be Reordered
Processor 0 Processor 1
rep:stosd [ _x] mov r1, [ _z]
mov r2, [ _y]
Initially on processor 0: EAX == 1, ECX==128, ES:EDI ==_x
Initially [_x] to 511[_x]== 0, _x <= _y < _z < _x+512
r1 == 1 and r2 == 0 is allowed