Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 23
Documentation Changes
BSWAP—Byte Swap
Instruction Operand Encoding
...
BT—Bit Test
Instruction Operand Encoding
...
Opcode Instruction Op/
En
64-bit
Mode
Compat/
Leg Mode
Description
0F C8+rd BSWAP r32 A Valid* Valid Reverses the byte order of
a 32-bit register.
REX.W + 0F
C8+rd
BSWAP r64 A Valid N.E. Reverses the byte order of
a 64-bit register.
NOTES:
* See IA-32 Architecture Compatibility section below.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A reg (r, w) NA NA NA
Opcode Instruction Op/
En
64-bit
Mode
Compat/
Leg Mode
Description
0F A3 BT r/m16, r16 A Valid Valid Store selected bit in CF flag.
0F A3 BT r/m32, r32 A Valid Valid Store selected bit in CF flag.
REX.W + 0F A3 BT r/m64, r64 A Valid N.E. Store selected bit in CF flag.
0F BA /4 ib BT r/m16, imm8 B Valid Valid Store selected bit in CF flag.
0F BA /4 ib BT r/m32, imm8 B Valid Valid Store selected bit in CF flag.
REX.W + 0F BA
/4 ib
BT r/m64, imm8 B Valid N.E. Store selected bit in CF flag.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:r/m (r) ModRM:reg (r) NA NA
B ModRM:r/m (r) imm8 NA NA