Specifications

Intel
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64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 229
Documentation Changes
5. Updates to Chapter 8, Volume 3A
Change bars show changes to Chapter 8 of the Intel
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64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 3A: System Programming Guide, Part 1.
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8.1 LOCKED ATOMIC OPERATIONS
The 32-bit IA-32 processors support locked atomic operations on locations in system
memory. These operations are typically used to manage shared data structures (such as
semaphores, segment descriptors, system segments, or page tables) in which two or
more processors may try simultaneously to modify the same field or flag. The processor
uses three interdependent mechanisms for carrying out locked atomic operations:
• Guaranteed atomic operations
• Bus locking, using the LOCK# signal and the LOCK instruction prefix
• Cache coherency protocols that ensure that atomic operations can be carried out on
cached data structures (cache lock); this mechanism is present in the Pentium 4,
Intel Xeon, and P6 family processors
These mechanisms are interdependent in the following ways. Certain basic memory
transactions (such as reading or writing a byte in system memory) are always guaran-
teed to be handled atomically. That is, once started, the processor guarantees that the
operation will be completed before another processor or bus agent is allowed access to
the memory location. The processor also supports bus locking for performing selected
memory operations (such as a read-modify-write operation in a shared area of memory)
that typically need to be handled atomically, but are not automatically handled this way.
Because frequently used memory locations are often cached in a processor’s L1 or L2
caches, atomic operations can often be carried out inside a processor’s caches without
asserting the bus lock. Here the processor’s cache coherency protocols ensure that other
processors that are caching the same memory locations are managed properly while
atomic operations are performed on cached memory locations.
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8.1.1 Guaranteed Atomic Operations
The Intel486 processor (and newer processors since) guarantees that the following basic
memory operations will always be carried out atomically:
• Reading or writing a byte
• Reading or writing a word aligned on a 16-bit boundary
• Reading or writing a doubleword aligned on a 32-bit boundary
The Pentium processor (and newer processors since) guarantees that the following addi-
tional memory operations will always be carried out atomically:
• Reading or writing a quadword aligned on a 64-bit boundary
• 16-bit accesses to uncached memory locations that fit within a 32-bit data bus
The P6 family processors (and newer processors since) guarantee that the following
additional memory operation will always be carried out atomically: