Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 226
Documentation Changes
In some cases, the consequences of delayed invalidation may not affect software
adversely. For example, when freeing a portion of the linear-address space (by marking
paging-structure entries “not present”), invalidation using INVLPG may be delayed if
software does not re-allocate that portion of the linear-address space or the memory
that had been associated with it. However, because of speculative execution (or errant
software), there may be accesses to the freed portion of the linear-address space before
the invalidations occur. In this case, the following can happen:
• Reads can occur to the freed portion of the linear-address space. Therefore, invali-
dation should not be delayed for an address range that has read side effects.
• The processor may retain entries in the TLBs and paging-structure caches for an
extended period of time. Software should not assume that the processor will not use
entries associated with a linear address simply because time has passed.
• As noted in Section 4.10.2.1, the processor may create an entry in a paging-
structure cache even if there are no translations for any linear address that might
use that entry. Thus, if software has marked “not present” all entries in page table,
the processor may subsequently create a PDE-cache entry for the PDE that
references that page table (assuming that the PDE itself is marked “present”).
• If software attempts to write to the freed portion of the linear-address space, the
processor might not generate a page fault. (Such an attempt would likely be the
result of a software error.) For that reason, the page frames previously associated
with the freed portion of the linear-address space should not be reallocated for
another purpose until the appropriate invalidations have been performed.
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