Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 225
Documentation Changes
• If a paging-structure entry is modified to change the accessed flag from 1 to 0,
failure to perform an invalidation may result in the processor not setting that bit in
response to a subsequent access to a linear address whose translation uses the
entry. Software cannot interpret the bit being clear as an indication that such an
access has not occurred.
• If software modifies a paging-structure entry that identifies the final physical
address for a linear address (either a PTE or a paging-structure entry in which the PS
flag is 1) to change the dirty flag from 1 to 0, failure to perform an invalidation may
result in the processor not setting that bit in response to a subsequent write to a
linear address whose translation uses the entry. Software cannot interpret the bit
being clear as an indication that such a write has not occurred.
• The read of a paging-structure entry in translating an address being used to fetch an
instruction may appear to execute before an earlier write to that paging-structure
entry if there is no serializing instruction between the write and the instruction fetch.
Note that the invalidating instructions identified in Section 4.10.3.1 are all serializing
instructions.
• Section 4.10.2.3 describes situations in which a single paging-structure entry may
contain information cached in multiple entries in the paging-structure caches.
Because all entries in these caches are invalidated by any execution of INVLPG, it is
not necessary to follow the modification of such a paging-structure entry by
executing INVLPG multiple times solely for the purpose of invalidating these multiple
cached entries. (It may be necessary to do so to invalidate multiple TLB entries.)
4.10.3.4 Delayed Invalidation
Required invalidations may be delayed under some circumstances. Software developers
should understand that, between the modification of a paging-structure entry and
execution of the invalidation instruction recommended in Section 4.10.3.2, the
processor may use translations based on either the old value or the new value of the
paging-structure entry. The following items describe some of the potential consequences
of delayed invalidation:
• If a paging-structure entry is modified to change from 1 to 0 the P flag from 1 to 0,
an access to a linear address whose translation is controlled by this entry may or
may not cause a page-fault exception.
• If a paging-structure entry is modified to change the R/W flag from 0 to 1, write
accesses to linear addresses whose translation is controlled by this entry may or may
not cause a page-fault exception.
• If a paging-structure entry is modified to change the U/S flag from 0 to 1, user-mode
accesses to linear addresses whose translation is controlled by this entry may or may
not cause a page-fault exception.
• If a paging-structure entry is modified to change the XD flag from 1 to 0, instruction
fetches from linear addresses whose translation is controlled by this entry may or
may not cause a page-fault exception.
As noted in Section 8.1.1, an x87 instruction or an SSE instruction that accesses data
larger than a quadword may be implemented using multiple memory accesses. If such
an instruction stores to memory and invalidation has been delayed, some of the
accesses may complete (writing to memory) while another causes a page-fault excep-
tion.
1
In this case, the effects of the completed accesses may be visible to software even
though the overall instruction caused a fault.
1. If the accesses are to different pages, this may occur even if invalidation has not been delayed.