Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 223
Documentation Changes
• PDPTE cache (IA-32e paging only).
1
Each PDPTE-cache entry is referenced by an
18-bit value and is used for linear addresses for which bits 47:30 have that value.
The entry contains information from the PML4E and PDPTE used to translate such
linear addresses:
— The physical address from the PDPTE (the address of the page directory). (No
PDPTE-cache entry is created for a PDPTE that maps a 1-GByte page.)
— The logical-AND of the R/W flags in the PML4E and the PDPTE.
— The logical-AND of the U/S flags in the PML4E and the PDPTE.
— The logical-OR of the XD flags in the PML4E and the PDPTE.
— The values of the PCD and PWT flags of the PDPTE.
The following items detail how a processor may use the PDPTE cache:
— If the processor has a PDPTE-cache entry for a linear address, it may use that
entry when translating the linear address (instead of the PML4E and the PDPTE in
memory).
— The processor does not create a PDPTE-cache entry unless the P flag is 1, the PS
flag is 0, and the reserved bits are 0 in the PML4E and the PDPTE in memory.
...
4.10.3.2 Recommended Invalidation
The following items provide some recommendations regarding when software should
perform invalidations:
• If software modifies a paging-structure entry that identifies the final page frame for
a page number (either a PTE or a paging-structure entry in which the PS flag is 1), it
should execute INVLPG for any linear address with a page number whose translation
uses that PTE.
2
(If the paging-structure entry may be used in the translation of
different page numbers — see Section 4.10.2.3 — software should execute INVLPG
for linear addresses with each of those page numbers; alternatively, it could use MOV
to CR3 or MOV to CR4.)
• If software modifies a paging-structure entry that references another paging
structure, it may use one of the following approaches depending upon the types and
number of translations controlled by the modified entry:
— Execute INVLPG for linear addresses with each of the page numbers with trans-
lations that would use the entry. However, if no page numbers that would use the
entry have translations (e.g., because the P flags are 0 in all entries in the paging
structure referenced by the modified entry), it remains necessary to execute
INVLPG at least once.
— Execute MOV to CR3 if the modified entry controls no global pages.
— Execute MOV to CR4 to modify CR4.PGE.
• If software using PAE paging modifies a PDPTE, it should reload CR3 with the
register’s current value to ensure that the modified PDPTE is loaded into the corre-
sponding PDPTE register (see Section 4.4.1).
1. With PAE paging, the PDPTEs are stored in internal, non-architectural registers. The operation of
these registers is described in Section 4.4.1 and differs from that described here.
2. One execution of INVLPG is sufficient even for a page with size greater than 4 KBytes.