Specifications
Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 222
Documentation Changes
while the lower bits come from the linear address of the access for which the translation
is created. There is no way for software to be aware that multiple translations for smaller
pages have been used for a large page.
If software modifies the paging structures so that the page size used for a 4-KByte range
of linear addresses changes, the TLBs may subsequently contain multiple translations for
the address range (one for each page size). A reference to a linear address in the
address range may use any of these translations. Which translation is used may vary
from one execution to another, and the choice may be implementation-specific.
4.10.1.4 Global Pages
The Intel-64 and IA-32 architectures also allow for global pages when the PGE flag
(bit 7) is 1 in CR4. If the G flag (bit 8) is 1 in a paging-structure entry that maps a page
(either a PTE or a paging-structure entry in which the PS flag is 1), any TLB entry cached
for a linear address using that paging-structure entry is considered to be global.
Because the G flag is used only in paging-structure entries that map a page, and because
information from such entries are not cached in the paging-structure caches, the global-
page feature does not affect the behavior of the paging-structure caches.
...
4.10.2.1 Caches for Paging Structures
A processor may support any or of all the following paging-structure caches:
• PML4 cache (IA-32e paging only). Each PML4-cache entry is referenced by a 9-bit
value and is used for linear addresses for which bits 47:39 have that value. The entry
contains information from the PML4E used to translate such linear addresses:
— The physical address from the PML4E (the address of the page-directory-pointer
table).
— The value of the R/W flag of the PML4E.
— The value of the U/S flag of the PML4E.
— The value of the XD flag of the PML4E.
— The values of the PCD and PWT flags of the PML4E.
The following items detail how a processor may use the PML4 cache:
— If the processor has a PML4-cache entry for a linear address, it may use that
entry when translating the linear address (instead of the PML4E in memory).
— The processor does not create a PML4-cache entry unless the P flag is 1 and all
reserved bits are 0 in the PML4E in memory.
— The processor does not create a PML4-cache entry unless the accessed flag is 1
in the PML4E in memory; before caching a translation, the processor sets the
accessed flag if it is not already 1.
— The processor may create a PML4-cache entry even if there are no translations
for any linear address that might use that entry (e.g., because the P flags are 0
in all entries in the referenced page-directory-pointer table).
— If the processor creates a PML4-cache entry, the processor may retain it
unmodified even if software subsequently modifies the corresponding PML4E in
memory.