Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 221
Documentation Changes
— If the translation does use a PTE, the page size is 4 KBytes and the page number
comprises bits 47:12 of the linear address.
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4.10.1.2 Caching Translations in TLBs
The processor may accelerate the paging process by caching individual translations in
translation lookaside buffers (TLBs). Each entry in a TLB is an individual translation.
Each translation is referenced by a page number. It contains the following information
from the paging-structure entries used to translate linear addresses with the page
number:
• The physical address corresponding to the page number (the page frame).
• The access rights from the paging-structure entries used to translate linear
addresses with the page number (see Section 4.6):
— The logical-AND of the R/W flags.
— The logical-AND of the U/S flags.
— The logical-OR of the XD flags (necessary only if IA32_EFER.NXE = 1).
• Attributes from a paging-structure entry that identifies the final page frame for the
page number (either a PTE or a paging-structure entry in which the PS flag is 1):
— The dirty flag (see Section 4.8).
— The memory type (see Section 4.9).
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4.10.1.3 Details of TLB Use
Because the TLBs cache only valid translations, there can be a TLB entry for a page
number only if the P flag is 1 and the reserved bits are 0 in each of the paging-structure
entries used to translate that page number. In addition, the processor does not cache a
translation for a page number unless the accessed flag is 1 in each of the paging-struc-
ture entries used during translation; before caching a translation, the processor sets any
of these accessed flags that is not already 1.
The processor may cache translations required for prefetches and for accesses that are
a result of speculative execution that would never actually occur in the executed code
path.
If the page number of a linear address corresponds to a TLB entry, the processor may
use that TLB entry to determine the page frame, access rights, and other attributes for
accesses to that linear address. In this case, the processor may not actually consult the
paging structures in memory. The processor may retain a TLB entry unmodified even if
software subsequently modifies the relevant paging-structure entries in memory. See
Section 4.10.3.2 for how software can ensure that the processor uses the modified
paging-structure entries.
If the paging structures specify a translation using a page larger than 4 KBytes, some
processors may choose to cache multiple smaller-page TLB entries for that translation.
Each such TLB entry would be associated with a page number corresponding to the
smaller page size (e.g., bits 47:12 of a linear address with IA-32e paging), even though
part of that page number (e.g., bits 20:12) are part of the offset with respect to the page
specified by the paging structures. The upper bits of the physical address in such a TLB
entry are derived from the physical address in the PDE used to create the translation,