Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 220
Documentation Changes
The PAT is a 64-bit MSR (IA32_PAT; MSR index 277H) comprising eight (8) 8-bit entries
(entry i comprises bits 8i+7:8i of the MSR).
For any access to a physical address, the table combines the memory type specified for
that physical address by the MTRRs with a memory type selected from the PAT.
Table 11-11 in Section 11.12.3 specifies how a memory type is selected from the PAT.
Specifically, it comes from entry i of the PAT, where i is defined as follows:
• For an access to an entry in a paging structure whose address is in CR3 (e.g., the
PML4 table with IA-32e paging), i = 2*PCD+PWT, where the PCD and PWT values
come from CR3.
• For an access to a PDE with PAE paging, i = 2*PCD+PWT, where the PCD and PWT
values come from the relevant PDPTE register.
• For an access to a paging-structure entry X whose address is in another paging-
structure entry Y, i = 2*PCD+PWT, where the PCD and PWT values come from Y.
• For an access to the physical address that is the translation of a linear address, i =
4*PAT+2*PCD+PWT, where the PAT, PCD, and PWT values come from the relevant
PTE (if the translation uses a 4-KByte page), the relevant PDE (if the translation uses
a 2-MByte page or a 4-MByte page), or the relevant PDPTE (if the translation uses a
1-GByte page).
...
4.10.1.1 Page Numbers, Page Frames, and Page Offsets
Section 4.3, Section 4.4.2, and Section 4.5 give details of how the different paging
modes translate linear addresses to physical addresses. Specifically, the upper bits of a
linear address (called the page number) determine the upper bits of the physical
address (called the page frame); the lower bits of the linear address (called the page
offset) determine the lower bits of the physical address. The boundary between the
page number and the page offset is determined by the page size. Specifically:
• 32-bit paging:
— If the translation does not use a PTE (because CR4.PSE = 1 and the PS flag is 1
in the PDE used), the page size is 4 MBytes and the page number comprises
bits 31:22 of the linear address.
— If the translation does use a PTE, the page size is 4 KBytes and the page number
comprises bits 31:12 of the linear address.
•PAE paging:
— If the translation does not use a PTE (because the PS flag is 1 in the PDE used),
the page size is 2 MBytes and the page number comprises bits 31:21 of the linear
address.
— If the translation does uses a PTE, the page size is 4 KBytes and the page number
comprises bits 31:12 of the linear address.
• IA-32e paging:
— If the translation does not use a PDE (because the PS flag is 1 in the PDPTE
used), the page size is 1 GBytes and the page number comprises bits 47:30 of
the linear address.
— If the translation does use a PDE but does not uses a PTE (because the PS flag is
1 in the PDE used), the page size is 2 MBytes and the page number comprises
bits 47:21 of the linear address.