Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 219
Documentation Changes
4.7 PAGE-FAULT EXCEPTIONS
Accesses using linear addresses may cause page-fault exceptions (#PF; exception
14). An access to a linear address may cause page-fault exception for either of two
reasons: (1) there is no valid translation for the linear address; or (2) there is a valid
translation for the linear address, but its access rights do not permit the access.
As noted in Section 4.3, Section 4.4.2, and Section 4.5, there is no valid translation for a
linear address if the translation process for that address would use a paging-structure
entry in which the P flag (bit 0) is 0 or one that sets a reserved bit. If there is a valid
translation for a linear address, its access rights are determined as specified in Section
4.6.
Figure 4-12 illustrates the error code that the processor provides on delivery of a page-
fault exception. The following items explain how the bits in the error code describe the
nature of the page-fault exception:
•P flag (bit0).
This flag is 0 if there is no valid translation for the linear address because the P flag
was 0 in one of the paging-structure entries used to translate that address.
• W/R (bit 1).
If the access causing the page-fault exception was a write, this flag is 1; otherwise,
it is 0. This flag describes the access causing the page-fault exception, not the access
rights specified by paging.
• U/S (bit 2).
If a user-mode (CPL= 3) access caused the page-fault exception, this flag is 1; it is 0
if a supervisor-mode (CPL < 3) access did so. This bit describes the access causing
the page-fault exception, not the access rights specified by paging.
...
4.8 ACCESSED AND DIRTY FLAGS
For any paging-structure entry that is used during linear-address translation, bit 5 is the
accessed flag. For paging-structure entries that map a page (as opposed to referencing
another paging structure), bit 6 is the dirty flag. These flags are provided for use by
memory-management software to manage the transfer of pages and paging structures
into and out of physical memory.
Whenever the processor uses a paging-structure entry as part of linear-address transla-
tion, it sets the accessed flag in that entry (if it is not already set).
Whenever there is a write to a linear address, the processor sets the dirty flag (if it is
not already set) in the paging-structure entry that identifies the final physical address
for the linear address (either a PTE or a paging-structure entry in which the PS flag is
1).
...
4.9.2 Paging and Memory Typing When the PAT is Supported
(Pentium III and More Recent Processor Families)
If the PAT is supported, paging contributes to memory typing in conjunction with the PAT
and the memory-type range registers (MTRRs) as specified in Table 11-7 in Section
11.5.2.2.