Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 217
Documentation Changes
— Bits 51:12 are from the PDPTE.
— Bits 11:3 are bits 29:21 of the linear address.
— Bits 2:0 are all 0
...
If a paging-structure entry’s P flag (bit 0) is 0 or if the entry sets any reserved bit, the
entry is used neither to reference another paging-structure entry nor to map a page. A
reference using a linear address whose translation would use such a paging-structure
entry causes a page-fault exception (see Section 4.7).
The following bits are reserved with IA-32e paging:
• If the P flag of a paging-structure entry is 1, bits 51:MAXPHYADDR are reserved.
• If the P flag of a PML4E is 1, the PS flag is reserved.
• If 1-GByte pages are not supported and the P flag of a PDPTE is 1, the PS flag is
reserved.
1
• If the P flag and the PS flag of a PDPTE are both 1, bits 29:13 are reserved.
• If the P flag and the PS flag of a PDE are both 1, bits 20:13 are reserved.
If IA32_EFER.NXE = 0 and the P flag of a paging-structure entry is 1, the XD flag
(bit 63) is reserved.
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1. See Section 4.1.4 for how to determine whether 1-GByte pages are supported.