Specifications
Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 216
Documentation Changes
— Bits 51:30 are from the PDPTE.
— Bits 29:0 are from the original linear address.
• If the PDE’s PS flag is 0, a 4-KByte naturally aligned page directory is located at the
physical address specified in bits 51:12 of the PDPTE (see Table 4-15). A page
directory comprises 512 64-bit entries (PDEs). A PDE is selected using the physical
address defined as follows:
63 (XD) If IA32_EFER.NXE = 1, execute-disable (if 1, instruction fetches are not allowed
from the 1-GByte page controlled by this entry; see Section 4.6); otherwise,
reserved (must be 0)
NOTES:
1. The PAT is supported on all processors that support IA-32e paging.
Table 4-15 Format of an IA-32e Page-Directory-Pointer-Table Entry (PDPTE) that
References a Page Directory
Bit
Position(s)
Contents
0 (P) Present; must be 1 to reference a page directory
1 (R/W) Read/write; if 0, writes may not be allowed to the 1-GByte region controlled by
this entry (depends on CPL and CR0.WP; see Section 4.6)
2 (U/S) User/supervisor; if 0, accesses with CPL=3 are not allowed to the 1-GByte region
controlled by this entry (see Section 4.6)
3 (PWT) Page-level write-through; indirectly determines the memory type used to access
the page directory referenced by this entry (see Section 4.9)
4 (PCD) Page-level cache disable; indirectly determines the memory type used to access
the page directory referenced by this entry (see Section 4.9)
5 (A) Accessed; indicates whether this entry has been used for linear-address
translation (see Section 4.8)
6Ignored
7 (PS) Page size; must be 0 (otherwise, this entry maps a 1-GByte page; see Table 4-14)
11:8 Ignored
(M–1):12 Physical address of 4-KByte aligned page directory referenced by this entry
51:M Reserved (must be 0)
62:52 Ignored
63 (XD) If IA32_EFER.NXE = 1, execute-disable (if 1, instruction fetches are not allowed
from the 1-GByte region controlled by this entry; see Section 4.6); otherwise,
reserved (must be 0)
Table 4-14 Format of an IA-32e Page-Directory-Pointer-Table Entry (PDPTE) that Maps
a 1-GByte Page (Continued)
Bit
Position(s)
Contents