Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 214
Documentation Changes
4.5 IA-32E PAGING
A logical processor uses IA-32e paging if CR0.PG = 1, CR4.PAE = 1, and
IA32_EFER.LME = 1. With IA-32e paging, linear address are translated using a hierarchy
of in-memory paging structures located using the contents of CR3. IA-32e paging trans-
lates 48-bit linear addresses to 52-bit physical addresses.
1
Although 52 bits corresponds
to 4 PBytes, linear addresses are limited to 48 bits; at most 256 TBytes of linear-address
space may be accessed at any given time.
IA-32e paging uses a hierarchy of paging structures to produce a translation for a linear
address. CR3 is used to locate the first paging-structure, the PML4 table. Table 4-12
illustrates how CR3 is used with IA-32e paging.
IA-32e paging may map linear addresses to 4-KByte pages, 2-MByte pages, or 1-GByte
pages.
2
Figure 4-8 illustrates the translation process when it produces a 4-KByte page;
Figure 4-9 covers the case of a 2-MByte page, and Figure 4-10 the case of a 1-GByte
page. The following items describe the IA-32e paging process in more detail as well has
how the page size is determined:
• A 4-KByte naturally aligned page-directory-pointer table is located at the physical
address specified in bits 51:12 of the PML4E (see Table 4-13). A page-directory-
pointer table comprises 512 64-bit entries (PDPTEs). A PDPTE is selected using the
physical address defined as follows:
— Bits 51:12 are from the PML4E.
— Bits 11:3 are bits 38:30 of the linear address.
— Bits 2:0 are all 0.
...
1. If MAXPHYADDR < 52, bits in the range 51:MAXPHYADDR will be 0 in any physical address used by
IA-32e paging. (The corresponding bits are reserved in the paging-structure entries.) See Section
4.1.4 for how to determine MAXPHYADDR.
Table 4-12 Use of CR3 with IA-32e Paging
Bit
Position(s)
Contents
2:0 Ignored
3 (PWT) Page-level write-through; indirectly determines the memory type used to access
the PML4 table during linear-address translation (see Section 4.9)
4 (PCD) Page-level cache disable; indirectly determines the memory type used to access
the PML4 table during linear-address translation (see Section 4.9)
11:5 Ignored
(M–1):12 Physical address of the 4-KByte aligned PML4 table used for linear-address
translation
1
NOTES:
1. M is an abbreviation for MAXPHYADDR, which is at most 52; see Section 4.1.4.
63:M Reserved (must be 0)
2. Not all processors support 1-GByte pages; see Section 4.1.4.