Specifications

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64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 213
Documentation Changes
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Table 4-8. Format of a PAE Page-Directory-Pointer-Table Entry (PDPTE)
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3. Reserved fields must be 0.
4. If IA32_EFER.NXE = 0 and the P flag of a PDE or a PTE is 1, the XD flag (bit 63) is reserved.
Bit
Position(s)
Contents
0 (P) Present; must be 1 to reference a page directory
2:1 Reserved (must be 0)
3 (PWT) Page-level write-through; indirectly determines the memory type used to access
the page directory referenced by this entry (see Section 4.9)
4 (PCD) Page-level cache disable; indirectly determines the memory type used to access
the page directory referenced by this entry (see Section 4.9)
8:5 Reserved (must be 0)
11:9 Ignored
(M–1):12 Physical address of 4-KByte aligned page directory referenced by this entry
1
NOTES:
1. M is an abbreviation for MAXPHYADDR, which is at most 52; see Section 4.1.4.
63:M Reserved (must be 0)