Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 211
Documentation Changes
Paging structures are given different names based their uses in the translation process.
Table 4-2 gives the names of the different paging structures. It also provides, for each
structure, the source of the physical address used to locate it (CR3 or a different paging-
structure entry); the bits in the linear address used to select an entry from the structure;
and details of about whether and how such an entry can map a page.
...
Table 4-2 Paging Structures in the Different Paging Modes
...
4.4.1 PDPTE Registers
When PAE paging is used, CR3 references the base of a 32-Byte page-directory-
pointer table. Table 4-8 illustrates how CR3 is used with PAE paging.
Paging
Structure
Entry
Name
Paging Mode
Physical
Address of
Structure
Bits
Selecting
Entry
Page Mapping
PML4 table PML4E
32-bit, PAE N/A
IA-32e CR3 47:39 N/A (PS must be 0)
Page-directory-
pointer table
PDPTE
32-bit N/A
PAE CR3 31:30 N/A (PS must be 0)
IA-32e PML4E 38:30 1-GByte page if PS=1
1
NOTES:
1. Not all processors allow the PS flag to be 1 in PDPTEs; see Section 4.1.4 for how to determine
whether 1-GByte pages are supported.
Page directory PDE
32-bit CR3 31:22 4-MByte page if PS=1
2
2. 32-bit paging ignores the PS flag in a PDE (and uses the entry to reference a page table) unless
CR4.PSE = 1. Not all processors allow CR4.PSE to be 1; see Section 4.1.4 for how to determine
whether 4-MByte pages are supported with 32-bit paging.
PAE, IA-32e PDPTE 29:21 2-MByte page if PS=1
Page table PTE
32-bit
PDE
21:12 4-KByte page
PAE, IA-32e 20:12 4-KByte page
Table 4-8 Use of CR3 with PAE Paging
Bit
Position(s)
Contents
4:0 Ignored
31:5 Physical address of the 32-Byte aligned page-directory-pointer table used for
linear-address translation
63:32 Ignored (these bits exist only on processors supporting the Intel-64 architecture)