Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 210
Documentation Changes
said to reference the other paging structure; in the latter, the entry is said to map a
page.
The first paging structure used for any translation is located at the physical address in
CR3. A linear address is translated using the following iterative procedure. A portion of
the linear address (initially the uppermost bits) select an entry in a paging structure
(initially the one located using CR3). If that entry references another paging structure,
the process continues with that paging structure and with the portion of the linear
address immediately below that just used. If instead the entry maps a page, the process
completes: the physical address in the entry is that of the page frame and the remaining
lower portion of the linear address is the page offset.
The following items give an example for each of the three paging modes (each example
locates a 4-KByte page frame):
• With 32-bit paging, each paging structure comprises 1024 = 2
10
entries. For this
reason, the translation process uses 10 bits at a time from a 32-bit linear address.
Bits 31:22 identify the first paging-structure entry and bits 21:12 identify a second.
The latter identifies the page frame. Bits 11:0 of the linear address are the page
offset within the 4-KByte page frame. (See Figure 4-2 for an illustration.)
• With PAE paging, the first paging structure comprises only 4 = 2
2
entries. Translation
thus begins by using bits 31:30 from a 32-bit linear address to identify the first
paging-structure entry. Other paging structures comprise 512 =2
9
entries, so the
process continues by using 9 bits at a time. Bits 29:21 identify a second paging-
structure entry and bits 20:12 identify a third. This last identifies the page frame.
(See Figure 4-5 for an illustration.)
• With IA-32e paging, each paging structure comprises 512 = 2
9
entries and
translation uses 9 bits at a time from a 48-bit linear address. Bits 47:39 identify the
first paging-structure entry, bits 38:30 identify a second, bits 29:21 a third, and
bits 20:12 identify a fourth. Again, the last identifies the page frame. (See
Figure 4-8 for an illustration.)
The translation process in each of the examples above completes by identifying a page
frame. However, the paging structures may be configured so that translation terminates
before doing so. This occurs if process encounters a paging-structure entry that is
marked “not present” (because its P flag — bit 0 — is clear) or in which a reserved bit is
set. In this case, there is no translation for the linear address; an access to that address
causes a page-fault exception (see Section 4.7).
In the examples above, a paging-structure entry maps a page with 4-KByte page frame
when only 12 bits remain in the linear address; entries identified earlier always reference
other paging structures. That may not apply in other cases. The following items identify
when an entry maps a page and when it references another paging structure:
• If more than 12 bits remain in the linear address, bit 7 (PS — page size) of the
current paging-structure entry is consulted. If the bit is 0, the entry references
another paging structure; if the bit is 1, the entry maps a page.
• If only 12 bits remain in the linear address, the current paging-structure entry
always maps a page (bit 7 is used for other purposes).
If a paging-structure entry maps a page when more than 12 bits remain in the linear
address, the entry identifies a page frame larger than 4 KBytes. For example, 32-bit
paging uses the upper 10 bits of a linear address to locate the first paging-structure
entry; 22 bits remain. If that entry maps a page, the page frame is 2
22
Bytes = 4
MBytes. 32-bit paging supports 4-MByte pages if CR4.PSE = 1. PAE paging and IA-32e
paging support 2-MByte pages (regardless of the value of CR4.PSE). IA-32e paging may
support 1-GByte pages (see Section 4.1.4).