Specifications

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64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 209
Documentation Changes
• PAT: page-attribute table.
If CPUID.01H:EDX.PAT [bit 16] = 1, the 8-entry page-attribute table (PAT) is
supported. When the PAT is supported, three bits in certain paging-structure entries
select a memory type (used to determine type of caching used) from the PAT (see
Section 4.9).
• PSE-36: 36-Bit page size extension.
If CPUID.01H:EDX.PSE-36 [bit 17] = 1, the PSE-36 mechanism is supported,
indicating that translations using 4-MByte pages with 32-bit paging may produce
physical addresses with more than 32 bits (see Section 4.3).
• NX: execute disable.
If CPUID.80000001H:EDX.NX [bit 20] = 1, IA32_EFER.NXE may be set to 1,
allowing PAE paging and IA-32e paging to disable execute access to selected pages
(see Section 4.6). (Processors that do not support CPUID function 80000001H do not
allow IA32_EFER.NXE to be set to 1.)
• Page1GB: 1-GByte pages.
If CPUID.80000001H:EDX.Page1GB [bit 26] = 1, 1-GByte pages are supported with
IA-32e paging (see Section 4.5).
• LM: IA-32e mode support.
If CPUID.80000001H:EDX.LM [bit 29] = 1, IA32_EFER.LME may be set to 1,
enabling IA-32e paging. (Processors that do not support CPUID function 80000001H
do not allow IA32_EFER.LME to be set to 1.)
• CPUID.80000008H:EAX[7:0] reports the physical-address width supported by the
processor. (For processors that do not support CPUID function 80000008H, the width
is generally 36 if CPUID.01H:EDX.PAE [bit 6] = 1 and 32 otherwise.) This width is
referred to as MAXPHYADDR. MAXPHYADDR is at most 52.
• CPUID.80000008H:EAX[15:8] reports the linear-address width supported by the
processor. Generally, this value is 48 if CPUID.80000001H:EDX.LM [bit 29] = 1 and
32 otherwise. (Processors that do not support CPUID function 80000008H, support a
linear-address width of 32.)
...
4.2 HIERARCHICAL PAGING STRUCTURES: AN OVERVIEW
All three paging modes translate linear addresses use hierarchical paging structures.
This section provides an overview of their operation. Section 4.3, Section 4.4, and
Section 4.5 provide details for the three paging modes.
Every paging structure is 4096 Bytes in size and comprises a number of individual
entries. With 32-bit paging, each entry is 32 bits (4 bytes); there are thus 1024 entries
in each structure. With PAE paging and IA-32e paging, each entry is 64 bits (8 bytes);
there are thus 512 entries in each structure. (PAE paging includes one exception, a
paging structure that is 32 bytes in size, containing 4 64-bit entries.)
The processor uses the upper portion of a linear address to identify a series of paging-
structure entries. The last of these entries identifies the physical address of the region to
which the linear address translates (called the page frame). The lower portion of the
linear address (called the page offset) identifies the specific address within that region
to which the linear address translates.
Each paging-structure entry contains a physical address, which is either the address of
another paging structure or the address of a page frame. In the first case, the entry is