Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 203
Documentation Changes
XCHG—Exchange Register/Memory with Register
Instruction Operand Encoding
...
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
90+rw XCHG AX, r16 A Valid Valid Exchange r16 with AX.
90+rw XCHG r16, AX B Valid Valid Exchange AX with r16.
90+rd XCHG EAX, r32 A Valid Valid Exchange r32 with EAX.
REX.W + 90+rd XCHG RAX, r64 A Valid N.E. Exchange r64 with RAX.
90+rd XCHG r32, EAX B Valid Valid Exchange EAX with r32.
REX.W + 90+rd XCHG r64, RAX B Valid N.E. Exchange RAX with r64.
86 /r XCHG r/m8, r8 C Valid Valid Exchange r8 (byte register)
with byte from r/m8.
REX + 86 /r XCHG r/m8*, r8* C Valid N.E. Exchange r8 (byte register)
with byte from r/m8.
86 /r XCHG r8, r/m8 D Valid Valid Exchange byte from r/m8
with r8 (byte register).
REX + 86 /r XCHG r8*, r/m8* D Valid N.E. Exchange byte from r/m8
with r8 (byte register).
87 /r XCHG r/m16, r16 C Valid Valid Exchange r16 with word
from r/m16.
87 /r XCHG r16, r/m16 D Valid Valid Exchange word from r/m16
with r16.
87 /r XCHG r/m32, r32 C Valid Valid Exchange r32 with
doubleword from r/m32.
REX.W + 87 /r XCHG r/m64, r64 C Valid N.E. Exchange r64 with
quadword from r/m64.
87 /r XCHG r32, r/m32 D Valid Valid Exchange doubleword from
r/m32 with r32.
REX.W + 87 /r XCHG r64, r/m64 D Valid N.E. Exchange quadword from
r/m64 with r64.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is
used: AH, BH, CH, DH.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A AX/EAX/RAX (r, w) reg (r, w) NA NA
B reg (r, w) AX/EAX/RAX (r, w) NA NA
C ModRM:r/m (r, w) ModRM:reg (r, w) NA NA
D ModRM:reg (r, w) ModRM:r/m (r, w) NA NA