Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 202
Documentation Changes
WRMSR—Write to Model Specific Register
Instruction Operand Encoding
...
XADD—Exchange and Add
Instruction Operand Encoding
...
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F 30 WRMSR A Valid Valid Write the value in EDX:EAX
to MSR specified by ECX.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
ANA NA NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F C0 /r XADD r/m8, r8 A Valid Valid Exchange r8 and r/m8; load
sum into r/m8.
REX + 0F C0 /r XADD r/m8*, r8* A Valid N.E. Exchange r8 and r/m8; load
sum into r/m8.
0F C1 /r XADD r/m16, r16 A Valid Valid Exchange r16 and r/m16;
load sum into r/m16.
0F C1 /r XADD r/m32, r32 A Valid Valid Exchange r32 and r/m32;
load sum into r/m32.
REX.W + 0F C1
/r
XADD r/m64, r64 A Valid N.E. Exchange r64 and r/m64;
load sum into r/m64.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is
used: AH, BH, CH, DH.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:r/m (r, w) ModRM:reg (r) NA NA