Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 194
Documentation Changes
SUBSD—Subtract Scalar Double-Precision Floating-Point Values
Instruction Operand Encoding
...
SUBSS—Subtract Scalar Single-Precision Floating-Point Values
Instruction Operand Encoding
...
SWAPGS—Swap GS Base Register
Instruction Operand Encoding
...
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
F2 0F 5C /r SUBSD xmm1,
xmm2/m64
A Valid Valid Subtracts the low double-
precision floating-point
values in xmm2/mem64
from xmm1.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
F3 0F 5C /r SUBSS xmm1,
xmm2/m32
A Valid Valid Subtract the lower single-
precision floating-point
values in xmm2/m32 from
xmm1.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F 01 /7 SWAPGS A Valid Invalid Exchanges the current GS
base register value with the
value contained in MSR
address C0000102H.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
ANA NA NA NA