Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 190
Documentation Changes
STI—Set Interrupt Flag
Instruction Operand Encoding
...
STMXCSR—Store MXCSR Register State
Instruction Operand Encoding
...
STOS/STOSB/STOSW/STOSD/STOSQ—Store String
Opcode* Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
FB STI A Valid Valid Set interrupt flag; external,
maskable interrupts enabled
at the end of the next
instruction.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
ANA NA NA NA
Opcode* Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F AE /3 STMXCSR m32 A Valid Valid Store contents of MXCSR
register to m32.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:r/m (w) NA NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
AA STOS m8 A Valid Valid For legacy mode, store AL at
address ES:(E)DI; For 64-bit
mode store AL at address
RDI or EDI.
AB STOS m16 A Valid Valid For legacy mode, store AX
at address ES:(E)DI; For 64-
bit mode store AX at
address RDI or EDI.
AB STOS m32 A Valid Valid For legacy mode, store EAX
at address ES:(E)DI; For 64-
bit mode store EAX at
address RDI or EDI.
REX.W + AB STOS m64 A Valid N.E. Store RAX at address RDI or
EDI.