Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 19
Documentation Changes
ANDNPS—Bitwise Logical AND NOT of Packed Single-Precision Floating-
Point Values
Instruction Operand Encoding
...
ARPL—Adjust RPL Field of Segment Selector
Instruction Operand Encoding
Description
Compares the RPL fields of two segment selectors. The first operand (the destination
operand) contains one segment selector and the second operand (source operand)
contains the other. (The RPL field is located in bits 0 and 1 of each operand.) If the RPL
field of the destination operand is less than the RPL field of the source operand, the ZF
flag is set and the RPL field of the destination operand is increased to match that of the
source operand. Otherwise, the ZF flag is cleared and no change is made to the destina-
tion operand. (The destination operand can be a word register or a memory location; the
source operand must be a word register.)
The ARPL instruction is provided for use by operating-system procedures (however, it
can also be used by applications). It is generally used to adjust the RPL of a segment
selector that has been passed to the operating system by an application program to
match the privilege level of the application program. Here the segment selector passed
to the operating system is placed in the destination operand and segment selector for
the application program’s code segment is placed in the source operand. (The RPL field
in the source operand represents the privilege level of the application program.) Execu-
tion of the ARPL instruction then ensures that the RPL of the segment selector received
by the operating system is no lower (does not have a higher privilege) than the privilege
level of the application program (the segment selector for the application program’s code
segment can be read from the stack following a procedure call).
This instruction executes as described in compatibility mode and legacy mode. It is not
encodable in 64-bit mode.
Opcode Instruction Op/
En
64-bit
Mode
Compat/
Leg Mode
Description
0F 55 /r ANDNPS xmm1,
xmm2/m128
A Valid Valid Bitwise logical AND NOT of
xmm2/m128 and xmm1.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA
Opcode Instruction Op/
En
64-bit
Mode
Compat/
Leg Mode
Description
63 /r ARPL r/m16, r16 AN. E. Valid Adjust RPL of r/m16 to not
less than RPL of r16.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:r/m (w) ModRM:reg (r) NA NA