Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 186
Documentation Changes
SHUFPD—Shuffle Packed Double-Precision Floating-Point Values
Instruction Operand Encoding
...
SHUFPS—Shuffle Packed Single-Precision Floating-Point Values
Instruction Operand Encoding
...
SIDT—Store Interrupt Descriptor Table Register
Instruction Operand Encoding
...
Opcode* Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
66 0F C6 /r ib SHUFPD xmm1,
xmm2/m128,
imm8
A Valid Valid Shuffle packed double-
precision floating-point
values selected by imm8
from xmm1 and
xmm2/m128 to xmm1.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) imm8 NA
Opcode* Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F C6 /r ib SHUFPS xmm1,
xmm2/m128,
imm8
A Valid Valid Shuffle packed single-
precision floating-point
values selected by imm8
from xmm1 and
xmm1/m128 to xmm1.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) imm8 NA
Opcode* Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F 01 /1 SIDT m A Valid Valid Store IDTR to m.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:r/m (w) NA NA NA