Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 185
Documentation Changes
Instruction Operand Encoding
...
SHRD—Double Precision Shift Right
Instruction Operand Encoding
...
Opcode* Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F A5 SHLD r/m32, r32,
CL
BValid Valid Shift r/m32 to left CL places
while shifting bits from r32
in from the right.
REX.W + 0F A5 SHLD r/m64, r64,
CL
BValid N.E. Shift r/m64 to left CL places
while shifting bits from r64
in from the right.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:r/m (w) ModRM:reg (r) imm8 NA
B ModRM:r/m (w) ModRM:reg (r) CL NA
Opcode* Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F AC SHRD r/m16, r16,
imm8
AValid Valid Shift r/m16 to right imm8
places while shifting bits
from r16 in from the left.
0F AD SHRD r/m16, r16,
CL
BValid Valid Shift r/m16 to right CL
places while shifting bits
from r16 in from the left.
0F AC SHRD r/m32, r32,
imm8
AValid Valid Shift r/m32 to right imm8
places while shifting bits
from r32 in from the left.
REX.W + 0F AC SHRD r/m64, r64,
imm8
AValid N.E. Shift r/m64 to right imm8
places while shifting bits
from r64 in from the left.
0F AD SHRD r/m32, r32,
CL
BValid Valid Shift r/m32 to right CL
places while shifting bits
from r32 in from the left.
REX.W + 0F AD SHRD r/m64, r64,
CL
BValid N.E. Shift r/m64 to right CL
places while shifting bits
from r64 in from the left.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:r/m (w) ModRM:reg (r) imm8 NA
B ModRM:r/m (w) ModRM:reg (r) CL NA