Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 184
Documentation Changes
Description
Performs a serializing operation on all store-to-memory instructions that were issued
prior the SFENCE instruction. This serializing operation guarantees that every store
instruction that precedes the SFENCE instruction in program order becomes globally
visible before any store instruction that follows the SFENCE instruction. The SFENCE
instruction is ordered with respect to store instructions, other SFENCE instructions, any
LFENCE and MFENCE instructions, and any serializing instructions (such as the CPUID
instruction). It is not ordered with respect to load instructions.
Weakly ordered memory types can be used to achieve higher processor performance
through such techniques as out-of-order issue, write-combining, and write-collapsing.
The degree to which a consumer of data recognizes or knows that the data is weakly
ordered varies among applications and may be unknown to the producer of this data.
The SFENCE instruction provides a performance-efficient way of ensuring store ordering
between routines that produce weakly-ordered results and routines that consume this
data.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
...
SGDT—Store Global Descriptor Table Register
Instruction Operand Encoding
...
SHLD—Double Precision Shift Left
Opcode* Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F 01 /0 SGDT m A Valid Valid Store GDTR to m.
NOTES:
* See IA-32 Architecture Compatibility section below.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:r/m (w) NA NA NA
Opcode* Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F A4 SHLD r/m16, r16,
imm8
AValid Valid Shift r/m16 to left imm8
places while shifting bits
from r16 in from the right.
0F A5 SHLD r/m16, r16,
CL
BValid Valid Shift r/m16 to left CL places
while shifting bits from r16
in from the right.
0F A4 SHLD r/m32, r32,
imm8
AValid Valid Shift r/m32 to left imm8
places while shifting bits
from r32 in from the right.
REX.W + 0F A4 SHLD r/m64, r64,
imm8
AValid N.E. Shift r/m64 to left imm8
places while shifting bits
from r64 in from the right.