Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 18
Documentation Changes
ANDPD—Bitwise Logical AND of Packed Double-Precision Floating-Point
Values
Instruction Operand Encoding
...
ANDPS—Bitwise Logical AND of Packed Single-Precision Floating-Point
Values
Instruction Operand Encoding
...
ANDNPD—Bitwise Logical AND NOT of Packed Double-Precision Floating-
Point Values
Instruction Operand Encoding
...
Opcode Instruction Op/
En
64-bit
Mode
Compat/
Leg Mode
Description
66 0F 54 /r ANDPD xmm1,
xmm2/m128
A Valid Valid Bitwise logical AND of
xmm2/m128 and xmm1.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA
Opcode Instruction Op/
En
64-bit
Mode
Compat/
Leg Mode
Description
0F 54 /r ANDPS xmm1,
xmm2/m128
A Valid Valid Bitwise logical AND of
xmm2/m128 and xmm1.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA
Opcode Instruction Op/
En
64-bit
Mode
Compat/
Leg Mode
Description
66 0F 55 /r ANDNPD xmm1,
xmm2/m128
A Valid Valid Bitwise logical AND NOT of
xmm2/m128 and xmm1.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA