Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 178
Documentation Changes
Instruction Operand Encoding
...
Opcode*** Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
REX + D0 /5 SHR r/m8**, 1 A Valid N.E. Unsigned divide r/m8 by 2,
once.
D2 /5 SHR r/m8, CL B Valid Valid Unsigned divide r/m8 by 2,
CL times.
REX + D2 /5 SHR r/m8**, CL B Valid N.E. Unsigned divide r/m8 by 2,
CL times.
C0 /5 ib SHR r/m8, imm8 C Valid Valid Unsigned divide r/m8 by 2,
imm8 times.
REX + C0 /5 ib SHR r/m8**, imm8 C Valid N.E. Unsigned divide r/m8 by 2,
imm8 times.
D1 /5 SHR r/m16, 1 A Valid Valid Unsigned divide r/m16 by 2,
once.
D3 /5 SHR r/m16, CL B Valid Valid Unsigned divide r/m16 by 2,
CL times
C1 /5 ib SHR r/m16, imm8 C Valid Valid Unsigned divide r/m16 by 2,
imm8 times.
D1 /5 SHR r/m32, 1 A Valid Valid Unsigned divide r/m32 by 2,
once.
REX.W + D1 /5 SHR r/m64, 1 A Valid N.E. Unsigned divide r/m64 by 2,
once.
D3 /5 SHR r/m32, CL B Valid Valid Unsigned divide r/m32 by 2,
CL times.
REX.W + D3 /5 SHR r/m64, CL B Valid N.E. Unsigned divide r/m64 by 2,
CL times.
C1 /5 ib SHR r/m32, imm8 C Valid Valid Unsigned divide r/m32 by 2,
imm8 times.
REX.W + C1 /5
ib
SHR r/m64, imm8 C Valid N.E. Unsigned divide r/m64 by 2,
imm8 times.
NOTES:
* Not the same form of division as IDIV; rounding is toward negative infinity.
** In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is
used: AH, BH, CH, DH.
***See IA-32 Architecture Compatibility section below.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:r/m (r, w) 1 NA NA
B ModRM:r/m (r, w) CL (r) NA NA
C ModRM:r/m (r, w) imm8 NA NA